`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:30:18 11/01/2011
// Design Name:   VGA_Sync_TEST
// Module Name:   C:/Users/Tyson/Documents/Verilog Projects/CPU svn proj 3710/trunk/vgasyn_test.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VGA_Sync_TEST
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module vgasyn_test;

	// Inputs
	reg clk;

	// Outputs
	wire hs;
	wire vs;
	wire [2:0] r;
	wire [2:0] g;
	wire [1:0] b;

	// Instantiate the Unit Under Test (UUT)
	VGA_Sync_TEST uut (
		.clk(clk), 
		.hs(hs), 
		.vs(vs), 
		.r(r), 
		.g(g), 
		.b(b)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		$monitor("r %d g %d b %d %x %x", r, g, b, hs, vs);
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
	
	always begin
	
	clk = ~clk;
	#1;
	end
      
endmodule

